1. Fields of the invention
The present invention relates to a debugging control system that uses inside-core events as trigger conditions and a method of the same, especially to a debugging control system that uses inside-core events as trigger conditions and a method of the same that adds cores designed for debugging into intellectual property (IP) during the design of integrated circuit for debugging of the IP after finishing production of the integrated circuit or the cores being written with programmable logic arrays. Moreover, values in registers of the core under debug are changed by a graphical interface software module so that the core under debug can be resumed to execute original programs according to the current internal state when the core under debug returns from a paused state to a normal state. The debugging time for the integrated circuit is dramatically reduced.
2. Descriptions of Related Art
Generally, a conventional debugging way triggered by events is built based on a debug and trace architecture. A plurality of watchpoints is inserted into a core and a debug and trace hardware gets signals of the watchpoints in the core and records the signals of the watchpoints for users to debug. In the debug and trace architecture, occurrences of the trigger events are detected by a fixed comparator and a finite-state machine with pre-defined signals. Although the occurrences of the trigger events can be detected correctly, the trigger events are unable to be modified due to the fixed signals and the comparator. It's quite hard to find out bugs in practice.
Moreover, the fixed comparator used has limits on the trigger events and this leads to insufficient comparison mode for the trigger event. In some research, event comparators are revealed to solve the problem of the comparison mode. However, not all signals in a core under debug (such as intellectual property (IP)) have the capability to reorganize the trigger events. The trigger signals are predetermined before manufacturing of the core under debug. Or the core under debug can be reconfigured by a plurality of multiplexers after being produced to get trigger signals. Thus the signals are difficult to be modified and used as trigger events and most of tracing and debugging is unable to record all signals inside the core. The debug and trace signals are only defined according to signals set in the debug core and memory size. Thus the data resolution obtained is not sufficient for users to find out where errors occurred.
After finishing production of the integrated circuit, the debug and trace method available now lacks observability and controllability of the signals in the IP. Thus circuit errors can only be observed through output/input ports of the integrated circuit during verification of the IP and there is no way to observe internal states of the core directly. Therefore it's difficult to find out and remove bugs of the integrated circuit. In order to reduce difficulties in verification of the core, designers add some cores designed for debug inside the integrated circuit so as to perform debugging efficiently. Refer to Taiwanese Pat. No. 1310461 “DEBUGGING SYSTEM AND SCAN-BASED DEBUGGING METHOD OF INTEGRATED CIRCUIT”, a scan-based debugging system and a method thereof are revealed. A scan-based integrated circuit includes a test interface, an in-circuit emulator, a core under debug and a memory. The in-circuit emulator is used to debug software of the system through the test interface. The core under debug has scan chain for reading out the state of every flip-flop. The state read out by the scan chain is saved in the memory and is transmitted to a computer through the test interface. The debugging method includes a plurality of steps. First stop operations of an integrated circuit in a normal mode. The states of a plurality of nodes of the core under debug are read out from a scan chain and saved in a memory. The states of the nodes are transmitted to a computer through a test interface. The integrated circuit further includes a scan-based debugging device coupled to the core under debug and the memory. The scan-based debugging device has a scan-based debugging controller. When the scan-based debugging controller is initialized, it checks whether the existing error condition is satisfied. The error conditions are written into the scan-based debugging controller. Once the existing condition is satisfied, the scan-based debugging controller stops the core under debug and enters a scan mode. However, the system and the method mentioned above has following disadvantages: (a) User are unable to select signals of the scan chains of the IP freely and use them as trigger signals and set trigger events. Thus they need to spend more time to find out bugs in the IP. (b) When the user is in a debug mode and is intended to go back to a normal mode, the core under debug is unable to turn back to the state before being paused. Thus the verification of the core under debug starts after system reset. The debugging time is increased. Thus there is room for improvement.